In layout design of a semiconductor device using a library of standard cells or the like, a technique used heretofore involves adopting the power-supply potential as the potential of a substrate or well or setting the substrate or well potential to a potential different from that of the power-supply voltage in order to control the threshold value of a MOS transistor. This technique relies upon a method in which a tap for supplying the well potential is placed within a cell or in which a tap cell is disposed appropriately between cell rows. The specification of Patent Document 1 describes an arrangement in which when a plurality of cells having impurity diffusion regions (which are electrically connected at mutually adjacent cells) for supplying a substrate or well potential different from the power-source potential are arranged out in series, a power supply reinforcing cell for providing reinforced power supply is disposed between mutually adjacent cells. The power supply reinforcing cell has an impurity diffusion region that electrically connects the impurity diffusion regions possessed by the cells adjacent thereto, and a power supply interconnect provided in an interconnect layer provided on an upper layer on the impurity diffusion region and is electrically connected to the impurity-diffusion region. A source diffusion region is connected to the interconnect line of a power-supply interconnect layer via a contact. Further, the specification of Patent Document 2 discloses a layout method of deciding the proper number of taps in a well and reducing the number of taps to make possible high-density integration.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2003-309178A
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2004-319855A
FIG. 12 is a diagram illustrating a typical example of the structure (twin-well structure) of a cell equipped with well-potential supply taps. An n-well 101 is provided with a source/drain 103 comprising a P+ diffusion region (referred to as a “P+ diffusion layer”), an a p-well 102 is provided with a source/drain 104 comprising an N+ diffusion region (referred to as a “N+ diffusion layer”). The n-well 101 and p-well 102 are provided with respective taps 106 and 107 comprising N+ and P+ diffusion regions, respectively, and are connected to power-supply (VDD) and ground (GND) interconnects (line) 110 and 111 arranged in a metal interconnect layer via contacts 112 and 113, respectively. The potentials of the n-well 101 and p-well 102 are fixed at the power supply VDD and ground GND. Further, the power-supply potential and ground potential are supplied to the sources of the source/drains 103 and 104 via interconnects 118 and 118 connected to the power supply (VDD) and ground (GND) interconnects 110 and 111, respectively. Gate electrodes 105 comprising polysilicon or the like are placed on a substrate between the diffusion regions of the source and drain via gate oxide films. Each of the two gate electrodes 105 forms a common gate of a P-channel MOS transistor within the n-well 101 and an N-channel MOS transistor within the p-well 102. A CMOS inverter is obtained by connecting the drain of the P-channel MOS transistor within the n-well 101 and the drain of the N-channel MOS transistor within the p-well 102.
In order to make it possible to supply any well potential to such a cell, it is necessary to design anew a cell that is capable of supplying tap potential that is independent of VDD and GND. There are also cases where use is made of a connection (referred to as a “batting connection” that is electrically short-circuited within the cell by disposing portions of diffusion regions (tap and source) of mutually different conductivity types in such a manner that they contact each other. With a batting connection, only the tap (source) is connected to metal interconnect for current feed, and potential is applied to the source (tap) from the tap (source) by the batting connection. Consequently, if it is attempted to alleviate new design load through a method of providing a layout that eliminates the tap within the cell and supplies any well potential separately, a cell having a batting connection is such that owing to elimination of the tap, the corresponding source floats electrically and the cell cannot function normally. Thus, it is necessary to design the cell afresh in any case. Design and verification require labor and greater burden.